An effective AS-FIFO design for Multiple Asynchronous Clock data transmission

This paper presents an effective design of a asynchronous FIFO circuit for multiple asynchronous clocks data transmission. The dual synchronization and gray code are proposed. According to experiments, the probability of metastability is reduced effectively. In the simulation the proposed circuits can operate at a clock rate of 256 MHz while in writing and 329 MHz in reading and is implemented in ALTERA Cyclone device. The simulation indicates that this design will have a wide application for multiple asynchronous clocks data transmission in SoPC or ASIC design.