DocumentCode :
3194862
Title :
Analysis of column compression multipliers
Author :
Bickerstaff, K. Andrea C ; Swartzlander, Earl E., Jr. ; Schulte, Michael J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear :
2001
fDate :
2001
Firstpage :
33
Lastpage :
39
Abstract :
Column compression multipliers are frequently used in high-performance computer systems due to their short worst case delay. This paper examines the area, delay, and power characteristics of Dadda (1965) and Wallace (1964) column compression multipliers in deep submicron technology. Our analysis shows that Wallace multipliers have slightly more area and approximately the same worst case delay as Dadda multipliers. It also shows the importance of considering parasitic capacitances when determining the delay of column compression multipliers, since parasitics can increase the delay of the multiplier by over 60%. As multiplier size increases, the ratio of power to area also increases, due to longer interconnect lines and increased glitching
Keywords :
digital arithmetic; multiplying circuits; column compression multipliers; deep submicron technology; delay; glitching; high-performance computer systems; interconnect lines; parasitic capacitance; worst case delay; CMOS technology; Counting circuits; Delay lines; Design automation; Frequency; Parasitic capacitance; Performance analysis; Pipeline processing; Power engineering computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on
Conference_Location :
Vail, CO
ISSN :
1063-6889
Print_ISBN :
0-7695-1150-3
Type :
conf
DOI :
10.1109/ARITH.2001.930101
Filename :
930101
Link To Document :
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