Title :
Network on Chip architecture for BP neural network
Author :
Dong, Yiping ; Watanabe, Takahiro
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu
Abstract :
Recently, networks-on-chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of artificial neural networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (back-propagation) and evaluated by network-on-chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.
Keywords :
backpropagation; network-on-chip; neural nets; BP neural network; artificial neural networks; network-on-chip architecture; on-chip communication problems; Application software; Artificial neural networks; Circuits; Computer architecture; Equations; Hardware; Network-on-a-chip; Neural networks; Neurons; Production systems;
Conference_Titel :
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location :
Fujian
Print_ISBN :
978-1-4244-2063-6
Electronic_ISBN :
978-1-4244-2064-3
DOI :
10.1109/ICCCAS.2008.4657930
