Title :
A hardware algorithm for computing reciprocal square root
Author_Institution :
Dept. of Inf. Eng., Nagoya Univ., Japan
Abstract :
A hardware algorithm for computing the reciprocal square root which appears frequently in multimedia and graphics applications is proposed. The reciprocal square root is computed by iteration of carry-propagation-free additions, shifts, and multiplications by one digit. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the digit set, etc. Each version of the algorithm can be implemented as a sequential (folded) circuit or a combinational (unfolded) circuit, which has a regular array structure suitable for VLSI
Keywords :
digital arithmetic; VLSI; carry-propagation-free additions; combinational circuit; digit set; folded circuit; graphics applications; hardware algorithm; multimedia; multiplications; radix; reciprocal square root; redundancy factor; regular array structure; sequential circuit; shifts; unfolded circuit; Circuits; Computer aided instruction; Difference equations; Engines; Graphics; Hardware; Microprocessors; Multimedia computing; Redundancy; Very large scale integration;
Conference_Titel :
Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on
Conference_Location :
Vail, CO
Print_ISBN :
0-7695-1150-3
DOI :
10.1109/ARITH.2001.930108
