Model Checker to FPGA Prototype Commmunication Bottleneck Issue

The main problem we met, when applying the TLC Model Checker to the verification of a Field Programmable Gate Array (FPGA)-based prototype [1], was the large delay introduced by the latency of the communication link. We have performed actual measurements on different FPGA platforms, and from these measurements we could elaborate a model or a set of mathematical formulas for the communication link. These suggested that we had to combine multiple packets in a single transfer to overcome the bottleneck issue. To do this, we had to anticipate TLC\´s future needs and obtain them automatically via transfers which are as large as possible and hence reduce the effect of link latency. For this purpose we made software and hardware memory (RAM) structures to buffer the packets going between TLC and the target implementation. We also had to develop strategies for more performance by improving these memories\´s organization and accessibility. An Embedded Reachability Analyzer And Invariant Checker (ERAIC) [2], part of our new methodology for Formal Verification of "Concrete" Digital Circuits, is essential. When combined with the memories, the ERAIC essentially eliminated the communication overhead. The mechanism relies on full state controllability and observability, and offers more performance, flexibility, portability, and furthermore, the possibility of checking invariants on the Implementation Under Test (IUT) before submitting it to the model checker.