DocumentCode :
3195152
Title :
Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking
Author :
Talupuru, Kesava R. ; Athi, Sanjai
fYear :
2011
fDate :
5-7 Dec. 2011
Firstpage :
5
Lastpage :
9
Abstract :
Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With the integration of multiple designs, various clock domains are introduced. In this paper, we present a solution for finding clock domain crossing glitch using a combination of formal verification and static timing analysis techniques. This paper also talks about leveraging a formal verification tool to do sequential equivalence checking between a buggy design and bug fixed design if CDC glitch is found in late design stages.
Keywords :
formal verification; program debugging; program diagnostics; software fault tolerance; system-on-chip; bug fixed design; buggy design; clock domain crossing glitch; formal verification; sequential equivalence checking; static timing analysis; system-on-a-chip; Clocks; Flip-flops; Formal verification; Logic gates; Synchronization; System-on-a-chip; clock domain crossing; formal verification; sequential equivalence checking; static timing analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microprocessor Test and Verification (MTV), 2011 12th International Workshop on
Conference_Location :
Austin, TX
ISSN :
1550-4093
Print_ISBN :
978-1-4577-2101-4
Type :
conf
DOI :
10.1109/MTV.2011.10
Filename :
6142332
Link To Document :
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