Title :
In order issue out-of-order execution floating-point coprocessor for CalmRISC32
Author :
Jeong, Cheol Ho ; Park, Woo Chan ; Han, Tack Don ; Kim, Sang Woo ; Lee, Moon Key
Author_Institution :
Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea
Abstract :
The CalmRISC32 FPU (Floating-Point Unit) is a RISC coprocessor for embedded system applications. It supports IEEE-754 standard single precision floating-point addition, floating-point subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, load, store, etc. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order, if constraints such as data dependency, resource conflict, and exception prediction are resolved. Standard cell-base design techniques were used to reduce design time and expense. The first prototype operated at approximately 70 MHz with the worst-case delay in gate level simulation
Keywords :
coprocessors; embedded systems; floating point arithmetic; reduced instruction set computing; CalmRISC32 Floating-Point Unit; IEEE-754 standard single precision operations; RISC coprocessor; cell-base design techniques; comparison; data dependency; embedded system applications; exception prediction; floating-point addition; floating-point division; floating-point multiplication; floating-point subtraction; format conversion; gate level simulation; in order issue out-of-order execution floating-point coprocessor; load; precise exception; resource conflict; rounding; rounding modes; store; worst-case delay; Coprocessors; Delay; Embedded system; Floating-point arithmetic; Hardware; Laboratories; Large scale integration; Microprocessors; Out of order; Pipelines;
Conference_Titel :
Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on
Conference_Location :
Vail, CO
Print_ISBN :
0-7695-1150-3
DOI :
10.1109/ARITH.2001.930119