Title :
A power-efficient 0.8 V, 9-bit, 20-MS/s pipelined ADC with opamp-shared loading-free architecture
Author :
Ou, Hsin-Hung ; Chang, Soon-Jyh ; Liu, Bin-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Abstract :
This paper demonstrates a 0.8-V, 9-bit, 20-MS/s pipelined ADC with only 0.58 pJ-Volts/step. A novel circuit architecture which merges opamp-sharing with loading-free structure is proposed. Such mechanism effectively reduces the number of opamps as well as the capacitive loading. In addition, an inverse-flip-around sample-and-hold with unity-feedback factor is employed which further reduces the power consumption. Simulation results using a 0.18 mum CMOS 1P6M process demonstrate the power consumption of this pipelined ADC is 4.5 mW which amounts to a figure-of-merit of 0.58 pJ-Volts/step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; sample and hold circuits; CMOS 1P6M process; capacitive loading; circuit architecture; figure-of-merit; inverse-flip-around sample-and-hold circuit; loading-free structure; opamp-shared loading-free architecture; pipelined ADC; pipelined analog-to-digital converter; power 4.5 mW; power consumption; size 0.18 mum; unity-feedback factor; voltage 0.8 V; CMOS process; Capacitors; Circuit simulation; Energy consumption; Feedback; Low voltage; Sampling methods; Switches; Switching circuits; Threshold voltage;
Conference_Titel :
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location :
Fujian
Print_ISBN :
978-1-4244-2063-6
Electronic_ISBN :
978-1-4244-2064-3
DOI :
10.1109/ICCCAS.2008.4657947
