Title :
Parallel prefix adder design
Author :
Beaumont-Smith, Andrew ; Lim, Cheng-Chew
Author_Institution :
Compaq Comput. Corp., MA, USA
Abstract :
The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 μm CMOS technology for a range of adder widths as a comparative study
Keywords :
VLSI; adders; digital arithmetic; logic design; trees (mathematics); CMOS technology; VLSI synthesis tool; area-delay design space; carry tree width; end-around carry adders; high-valency prefix cells; low logical depth; parallel prefix adder design; prefix adder carry tree design; prefix cell valency; reduced fan-out loading; repeated carry tree spacing; Adders; CMOS process; CMOS technology; Counting circuits; Equations; Floating-point arithmetic; Signal generators; Space technology; Technological innovation; Very large scale integration;
Conference_Titel :
Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on
Conference_Location :
Vail, CO
Print_ISBN :
0-7695-1150-3
DOI :
10.1109/ARITH.2001.930122
