A novel SRAM structure for leakage power suppression in 45nm technology

Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named dynamic standby mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45 nm technology model of BPTM (Berkeley predictive technology method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and gated-Vdd SRAM, respectively (Qin et al., 2005 and Powell et al., 2000). Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.