Title :
Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process
Author :
Liang, Dong-Shang ; Tai, Cheng-Chi ; Gan, Kwang-Jow ; Lin, Yi-Zhi
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Yun-Kan
Abstract :
A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35 mum SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (HBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; MOSFET; heterojunction bipolar transistors; integrated memory circuits; BiCMOS process; MOSFET; SiGe; heterojunction-bipolar-transistor; memory circuit; metal-oxide-semiconductor field-effect-transistor; multiple-valued memory design; negative differential resistance circuits; size 0.35 mum; BiCMOS integrated circuits; CMOS process; Circuit synthesis; Design engineering; Fabrication; Germanium silicon alloys; Heterojunction bipolar transistors; Silicon germanium; System-on-a-chip; Voltage;
Conference_Titel :
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location :
Fujian
Print_ISBN :
978-1-4244-2063-6
Electronic_ISBN :
978-1-4244-2064-3
DOI :
10.1109/ICCCAS.2008.4657954
