High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches

Proposed a way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches. It includes defining of amount of CMOS devices (in the same cluster) simultaneously toggling at the same place and following voltage droop analysis of whether amount of devices, belonging to the same cluster, toggle above the predefined threshold, all over the functional pattern(s). Additionally, we define clear guidelines to the implementation tools how constantly toggling CMOS devices like clock buffers, are expected to be placed in order to avoid PDN failures. Some examples of the proposed approach are provided.