Systolic realization for 2-D linear phase FIR decimators and interpolators

Two systolic structures for the realization of two-dimensional FIR linear-phase decimators and interpolators are presented. The structures are derived in terms of decimators only since an interpolator structure can be obtained by a direct transposition of the signal flow graph of the corresponding decimator. One of the systolic structures is found to have an advantage over the other structure in that its data flow is regular and so a straightforward commutation action is sufficient to decimate the input into the required sequences as needed by the computing arrays.<>