DocumentCode
3195947
Title
Implementation of an 8000 BPS CELP coder on a single TMS320C25 digital signal processor chip
Author
Bryden, Karen ; Brind´Amour, André ; Hassanein, Hisham
Author_Institution
Commun. Res. Centre, Ottawa, Ont., Canada
fYear
1989
fDate
1-2 June 1989
Firstpage
384
Lastpage
387
Abstract
The implementation of a code-excited linear-predictive coder on a single TMS320C25 digital signal processor is described. In this implementation, an excitation vector selected from a 32-entry waveform codebook drives a cascade of a single coefficient lag synthesis filter followed by a ten-coefficient format synthesis filter to produce good-quality speech at 8000 b/s.<>
Keywords
digital signal processing chips; encoding; filtering and prediction theory; speech analysis and processing; 32-entry waveform codebook; 8000 bit/s; CELP coder; TMS320C25; code-excited linear-predictive coder; digital signal processor chip; excitation vector; good-quality speech; single coefficient lag synthesis filter; speech coding; ten-coefficient format synthesis filter; Digital signal processors; Filters; Frequency; History; Reflection; Signal processing algorithms; Signal synthesis; Speech synthesis; Stochastic processes; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC, Canada
Type
conf
DOI
10.1109/PACRIM.1989.48382
Filename
48382
Link To Document