Title :
QuickPath Interconnect (QPI) design and analysis in high speed servers
Author :
Mutnury, Bhyrav ; Paglia, Frank ; Mobley, James ; Singh, Girish K. ; Bellomio, Ron
Author_Institution :
Enterprise Server Design, Dell, Dell Inc., Round Rock, TX, USA
Abstract :
Increase in processor speeds and recent advancements in processor performance through developments such as multi-core processing and simultaneous multi-threading (SMT) have resulted in a need for faster processor interconnect technology. The Intel® QuickPath Interconnect (QPI) is a high-speed, packetized, point-to-point interconnect used in Intel´s next generation of microprocessors. Compared to its predecessor front-side bus (FSB), it offers much higher bandwidth with low latency. In this paper, electrical design characteristics of a QPI interface are analyzed in a high-end rack or blade server application. Also, the electrical challenges faced in designing the QPI interface in a high-end server environment from a signal integrity perspective are discussed. Sensitivity analysis on various uncontrollable electrical parameters is performed to understand their impact on QPI interface.
Keywords :
integrated circuit interconnections; microprocessor chips; multi-threading; parallel processing; Intel QuickPath Interconnect; electrical design; high speed Interconnect; high speed server; multicore processing; packetized Interconnect; point-to-point interconnect; processor speed; sensitivity analysis; signal integrity; simultaneous multithreading; uncontrollable electrical parameter; Clocks; Impedance; Integrated circuit interconnections; Receivers; Routing; Servers; Topology; PCB material; channel loss; design of experiments; interconnect; via stub;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
DOI :
10.1109/EPEPS.2010.5642789
