Encoder design and its hardware implementation for q-ary LDPC codes

In order to implement an encoder of q-ary LDPC codes, the RU algorithm proposed in [1] is applied in encoder design of q-ary LDPC codes in this paper. A new preprocessing algorithm helping to producing sparser inverse matrix T^-1 is presented, which results in better tradeoff strategy between resources and throughput with proper implementation module in T^-1. The feasibility and effect of the algorithm is verified through a hardware implementation of a random 4-ary LDPC codes on a Xilinx spartan3s1500. The encoder runs at 129 MHz and has a throughput of 36.8 Msymbol/s, namely, 73.6 M codeword bits per second. Only by proper combination in preprocessing algorithm and architecture, it is found that the throughput beyond 100 Mb/s is also possible.