Optimization of FPGA design and implementation of timing recovery in DVB-S2

The design of timing recovery in DVB-S2 demodulator is a challenging issue, especially with the modulation scheme of high order amplitude and phase shift keying (APSK) and the very low signal to noise ratio (SNR) near Shannon limits. This paper presents an FPGA implementation scheme which meets the requirements of DVB-S2 system. Based on some comparison and analysis, Gardner algorithm is adopted as detector for its insensitiveness to carrier offset and modulation types, and cubic interpolator is employed for its high accuracy. Controller is also designed to restrain cycle slips and the implementation of loop filter is optimized to reduce truncation noise. The design is implemented in Altera Stratix II EP2S180 FPGA, working with other components of the demodulator. Software simulation results show that the performance loss introduced by timing recovery is negligible for all DVB-S2 modulation types, and the circuit provides reasonable symbol synchronization even when the signal to noise ratio (Eb/No) equals to -2 dB in FPGA tests.