Testing and simulation of wire bonding attach for higher current

The reliable semiconductor chip´s wire bonding is one of the basic steps for the receiving good quality of final electronic system as well suitable economical solution. This paper describes some results obtained during our research work concerning development of the test equipment for high current stress measurement, for standard CMOS technology. High current density and high temperature gradient, which evoke in electronic devices the thermo mechanical stress, are the major reliability concerns for the future generation of high density power electronics. The developed Multi Channel High Current Test System is a PC based, stand alone driver and measurement tool, which is intended for the above described reliability testing. The equipment is able to measure small changes in connection resistance during long term reliability tests, where the contact is stressed by current up to 10 A. For this purpose was designed and realized in AMIS CMOS 0.7 technology semiconductor test chip (Fig. 1) that enable to measure maximum charge of current for different types of wires and served for study of chip pads degradation during increasing current load. The chip that includes heating resistor for simulation of temperature conditions was mounted on both, organic (FR-4) and inorganic (alumina) substrate to investigate chip pads degradation. Wire bonding was performed with different Al wire diameters (25μm, 50μm, 150μm and 300 μm, as well ribbon 150 × 13μm) and current capacity was investigated. Currently with this experimental work the modeling and simulation of electrical (current density and potential distribution) and thermo mechanical stressing were implemented. There was applied ANSYS to make the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. The first object was determining the stress distribution in connection wires because the most probably crack of the wire is - - in the place with the maximal stress value. Next object is the investigation of the current distribution in wires. The theoretical results are compared with test data of real experiment. The final aim of this paper is to show how to assure reliability of semiconductor chip for power interconnection and how to increase durability of these structures in the practical use. This paper describes some results achieved in the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. A test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards is focused on investigation of interconnection reliability for semiconductor chips under high current regime until 10 A, or more.