A parallel implementation of MP3 decoding algorithm on Reconfigurable Computing systems

Author

Yin, Chongyong ; Yin, Shouyi ; Wei, Shaojun

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing

fYear

2008

fDate

25-27 May 2008

Firstpage

1378

Lastpage

1381

Abstract

This paper describes a reconfigurable computing system, which consists of a general-purpose ARM processor and reconfigurable cells array (RCA). A novel mapping mechanism which makes data-parallelism instructions operate on RCA has been proposed to map and implement MP3 audio decoding algorithm containing intrinsic data-parallelism operations. The communication interface between ARM processor and RCA is implemented efficiently using the standard ARM assembly language. With the standard ARM C compiler, the hybrid decoding source files in which assembly language embedded are compiled to standard ARM machine instructions. The average decoding time of each frame is improved to 17.9 ms, and enhanced approximately 10% to which decoding time per frame is 20 ms, when the sampling frequency and bit-rate are 44.1 KHZ and 128 kbps, respectively.

Keywords

assembly language; audio coding; compiler generators; ARM C compiler; ARM assembly language; MP3 audio decoding; general-purpose ARM processor; parallel implementation; reconfigurable cells array; reconfigurable computing systems; Assembly; Communication standards; Computer architecture; Concurrent computing; Decoding; Digital audio players; Field programmable gate arrays; Hardware; Microprocessors; Software maintenance;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on

Conference_Location

Fujian

Print_ISBN

978-1-4244-2063-6

Electronic_ISBN

978-1-4244-2064-3

Type

conf

DOI

10.1109/ICCCAS.2008.4658023

Filename

4658023