FPGA-based image compression for low-power Wireless Camera Sensor Networks

In this paper, a low-complexity image compression scheme for energy-constrained Wireless Camera Sensor Networks (WCSN) is presented and its hardware implementation cost for FPGA solution is evaluated. The main purpose of this FPGA circuit is to relieve the main microcontroller in the camera sensor node of the image compression tasks and to achieve highspeed and low-power image processing. The interest of our hardware solution is twofold. First, a fast zonal DCT algorithm is used to reduce the number of DCT coefficients in each block of the image to be computed, quantized and encoded. Second, compression settings can be changed at runtime in order to allow a dynamic adjustment of the trade-off between energy consumption and image distortion. The efficiency of the image compression scheme is validated through experimental results using FPGA platform.