Title :
A high purity, high speed direct digital synthesizer
Author :
Kent, Gary W. ; Sheng, Neng-Haung
Author_Institution :
Collins Avionics & Commun. Div., Rockwell Int. Corp., Cedar Rapids, IA, USA
fDate :
31 May-2 Jun 1995
Abstract :
A Direct Digital Synthesizer (DDS), that clocks at 500 MHz, has been constructed in a 70 pin hybrid circuit package that is 1.14×2.33×0.2 inches. Spectral purity is better than -55 dBc worst case spur, up to 245 MHz output frequency. TTL compatible, parallel lines are provided for 28 bits of frequency and 8 bits of phase control. The hybrid is based on two GaAs chips, a HBT digital to analog converter and a MESFET accumulator/ROM combination. Two silicon ECL chips are used for clock amplification and distribution. This allows an AC coupled sinusoidal input clock of 0 dBm nominal amplitude. Power dissipation is typically 5 watts using +5.0, -5.2, and -2.2 volt supplies. This paper describes the DDS architecture, design of the GaAs chips, and special problems encountered during development of the hybrid
Keywords :
III-V semiconductors; digital integrated circuits; direct digital synthesis; gallium arsenide; hybrid integrated circuits; 5 W; 500 MHz; GaAs; GaAs chips; HBT digital to analog converter; MESFET accumulator; ROM; clock; high speed direct digital synthesizer; hybrid circuit; silicon ECL chips; spectral purity; Circuits; Clocks; Digital-analog conversion; Frequency; Gallium arsenide; Heterojunction bipolar transistors; MESFETs; Packaging; Phase control; Synthesizers;
Conference_Titel :
Frequency Control Symposium, 1995. 49th., Proceedings of the 1995 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-2500-1
DOI :
10.1109/FREQ.1995.483904
