Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

Author

Ezawa, Hirokazu ; Togasaki, Takashi ; Migita, Tatsuo ; Yamashita, Soichi ; Inohara, Masahiro ; Koshio, Yasuhiro ; Fukuda, Masatoshi ; Miyata, Masahiro ; Nagamine, Koro ; Iijima, Tadashi

Author_Institution

Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan

fYear

2010

fDate

13-16 Sept. 2010

Firstpage

1

Lastpage

6

Abstract

Leading-edge LSI products with 40nm logic technology node and beyond are facing the issue of how higher memory bandwidth is reconciled with lower power consumption. Chip stacking of a logic chip on a large-scale DRAM chip, interconnected with each other by fine-pitch bumps, provides a solution to realize a power efficient SiP (System in Package). In this paper, the successful process integration of 10μm pitch Cu redistribution wiring and 40μm pitch SnCu micro-bumping on 300mm wafers, together with chip-on-chip (CoC) joining, has been described in an effort to relinquish embedded DRAM (eDRAM) SoC (System on Chip).

Keywords

DRAM chips; chip scale packaging; copper; embedded systems; fine-pitch technology; large scale integration; logic circuits; low-power electronics; system-in-package; system-on-chip; wiring; CoC joining; SoC; chiip stacking; chip-on-chip joining; copper redistribution wiring; eDRAM; embedded DRAM; fine pitch microbumping; fine-pitch bumps; large-scale DRAM chip; leading-edge LSI products; logic chip; logic technology node; lower power consumption; memory bandwidth; power efficient; process integration; system in package; system on chip; Atmospheric measurements; Films; Lead; Neodymium; Nickel; Random access memory; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Conference_Location

Berlin

Print_ISBN

978-1-4244-8553-6

Electronic_ISBN

978-1-4244-8554-3

Type

conf

DOI

10.1109/ESTC.2010.5642887

Filename

5642887