DocumentCode
3197877
Title
Fan-Out Wafer-Level Packaging with highly flexible design capabilities
Author
Kurita, Yoichiro ; Kimura, Takehiro ; Shibuya, Koujirou ; Kobayashi, Hiroaki ; Kawashiro, Fumiyoshi ; Motohashi, Norikazu ; Kawano, Masaya
fYear
2010
fDate
13-16 Sept. 2010
Firstpage
1
Lastpage
6
Abstract
We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed using 5.0 mm × 5.0 mm FO-WLP. This technology is suited for applications in extremely small microcomputer chip/system packaging for ubiquitous computing.
Keywords
microcontrollers; wafer level packaging; board-level reliability; fan-out wafer-level packaging technology; flexible design capability; land grid array; microcomputer chip packaging; microcomputer system packaging; microcontroller chip; multilayer fan-out redistribution layer; ubiquitous computing; Lead; Microcontrollers; Polyimides; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic System-Integration Technology Conference (ESTC), 2010 3rd
Conference_Location
Berlin
Print_ISBN
978-1-4244-8553-6
Electronic_ISBN
978-1-4244-8554-3
Type
conf
DOI
10.1109/ESTC.2010.5642888
Filename
5642888
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