A methodological approach for the minimization of self-interference effects in highly integrated transceiver SoCs

A design methodology is introduced, which is aimed at the minimization of the duration and costs associated with the productization of complex transceiver system-on-chip (SoC) solutions that typically exhibit self-interference problems once fabricated. Such products comprise extensive digital circuitry, mixed-signal functions, and sensitive RF blocks, creating high potential for self-interference within the SoC. The proposed design-for-interference-mitigation (DfIM) approach uses the existing on-chip processing and memory resources to effectively address these problems, thus eliminating the need for a hardware revision and saving the associated time and cost. Two implementation examples for this methodology in Digital RF Processor (DRP¿)-based wireless SoCs are shown to demonstrate the effectiveness of the approach.