Title :
When does a circuit really fail?
Author :
Ryan, J.T. ; Wei, L. ; Campbell, J.P. ; Southwick, R.G. ; Cheung, K.P. ; Oates, A.S. ; Wong, H.-S.P. ; Suehle, J.
Author_Institution :
Semicond. Electron. Div., NIST, Gaithersburg, MD, USA
Abstract :
An important stage in qualifying a new technology for full scale production is meeting reliability criteria. Unfortunately, conventional reliability qualification approaches utilize a “one size fits all” mentality which is intended to encompass all possible circuit applications. Furthermore, the reliability criteria are sometimes based on seemingly arbitrary device level parametric shifts and the choice of which parameter to utilize is crucial. The purpose of this paper is to introduce a “circuit aware” concept for reliability qualification. By taking into consideration circuit-level figures of merit, we demonstrate a methodology to establish device level reliability criteria that reflects the real world operation of devices in circuits. The methodology does not require any additional measurements or the fabrication of special test circuits. The beauty is in its simplicity, a simple transformation to solve an important problem.
Keywords :
SPICE; semiconductor device reliability; circuit aware concept; circuit-level figures of merit; device level reliability criteria; Degradation; Delay; Integrated circuit reliability; Qualifications; Stress;
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2011 IEEE International
Conference_Location :
South Lake Tahoe, CA
Print_ISBN :
978-1-4577-0113-9
DOI :
10.1109/IIRW.2011.6142583