Product dielectric reliability

We conducted TDDB test and Vrdb test on two different stressed cap layer (CESL, contact-etch-stop-layer) processes as a part of evaluation of 40 nm deep submicron technology for pMOS. Similar Weibull distributions including shape factor, temperature and voltage acceleration factors, were observed in TDDB between two processes. However, Vrdb results present far distinct extrinsic behavior between two processes indicating the incompleteness of TDDB test. An analytical methodology based on power law model for dielectric reliability is employed to quantitatively relate Vrdb Vbd with TDDB test for a product in lifetime scale. Lifetime derived from Vbd correlates well with the intrinsic TDDB distribution; nevertheless, lifetime represented by extrinsic Vbd distribution for higher cap stressed sample displayed a much weaker long tail end which was missing in TDDB test. Furthermore, efforts in finding correlation between initial gate leakage current and TTF is explored and discussed in detail.