DocumentCode :
3198877
Title :
Properties of high-k materials embedded in low temperature cofired ceramics
Author :
Bartsch, Heike ; Grieseler, Rolf ; Müller, Jens ; Barth, Stefan ; Pawlowski, Beate
Author_Institution :
Inst. for Micro- & Nanotechnol., Tech. Univ. Ilmenau, Ilmenau, Germany
fYear :
2010
fDate :
13-16 Sept. 2010
Firstpage :
1
Lastpage :
5
Abstract :
Buried capacitors in low temperature cofired ceramics (LTCC) enable increased package density, shorter interconnects and reduced assembly time. The implementation of local patches of (high-k) Sr-doped BaTiO3-tape into a commercial LTCC material (DuPont 951 GreenTape™) using pressure assisted sintering resulted in areal capacitance densities up to 100 pF/mm2 for 29 μm thick dielectric layers. The influence of the firing conditions, the number of refires and the capacitor assembly on the capacitance was investigated. The k-values range between 161 and 367, depending on sintering conditions and design. That indicates the presence of a permittivity gradient at the contact area between low- and high-k materials, which depends on the metallization geometry and peak temperature. The material distribution at the interface was investigated using EDX analysis to demonstrate the effect of the electrodes as barrier layers to prevent dielectric interactions. Embedded capacitors with a plate area of 5.29 mm2 possessed capacitances greater than 500 pF with tolerances of 8 %. This matches the requirements of class K. The insertion loss of rf-components remained below -15 dB up to 50 GHz, which indicates very good noise suppression behaviour. The capacitors are thus suited for decoupling in the close vicinity of integrated circuits in ceramic packages.
Keywords :
X-ray chemical analysis; barium compounds; buried layers; capacitors; ceramic packaging; firing (materials); high-k dielectric thin films; low-k dielectric thin films; metallisation; permittivity; sintering; strontium; BaTiO3:Sr; DuPont 951 GreenTape; EDX; LTCC; areal capacitance densities; assembly time; buried capacitors; capacitor assembly; ceramic packages; contact area; dielectric interactions; dielectric layers; embedded high-k materials; firing conditions; local patches; low temperature cofired ceramics; low-k materials; material distribution; metallization geometry; package density; permittivity gradient; pressure assisted sintering; size 29 mum; Artificial intelligence; Barium; Capacitors; Electrodes; Lead; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic System-Integration Technology Conference (ESTC), 2010 3rd
Conference_Location :
Berlin
Print_ISBN :
978-1-4244-8553-6
Electronic_ISBN :
978-1-4244-8554-3
Type :
conf
DOI :
10.1109/ESTC.2010.5642935
Filename :
5642935
Link To Document :
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