• DocumentCode
    3199217
  • Title

    Model based design workflow for FPGA compliance with DO-254 standard

  • Author

    Liu, Jie

  • Author_Institution
    Sch. of Phys. & Inf. Eng., Fuzhou Univ., Fuzhou, China
  • Volume
    2
  • fYear
    2012
  • fDate
    3-5 Aug. 2012
  • Firstpage
    1026
  • Lastpage
    1030
  • Abstract
    In order to meet a number of industries hardware that require high reliability and large amount of code, this paper gives a model-based design (MBD) workflow compliance with DO-254 standard for hardware development process. Taking the Digital down conversion (DDC) for example; this paper has described how to use the tool chain of Simulink, HDL Coder and Modelsim to complete the entire development process. In this way, we can build a DDC model starting from requirements analysis to functional verification and system testing of the model, fixed-point optimization, code generation, and then validation the DDC system on XUPV5 board in visual development environment. The entire process which starts from design concept to hardware implementation always focuses on the DDC model for continuous testing and verification. In this way, we can verify and validate the correctness of the design of DDC in three different levels, so that design flaws could be exhumed in the early stages of the development. The proposed solution is not only overcoming the flaws of low efficiency and difficulty of meeting the requirements in traditional methods of development, but also to avoid the potential risk in technology and market.
  • Keywords
    digital simulation; electronic engineering computing; field programmable gate arrays; logic design; optimisation; program compilers; standards; DDC; DO-254 standard; FPGA compliance; HDL coder; MBD; Modelsim; Simulink; XUPV5 board; code generation; digital down conversion; fixed-point optimization; functional verification; hardware development process; industries hardware; model-based design workflow; system testing; visual development environment; Calibration; Education; Field programmable gate arrays; GSM; Hardware; Standards; DO-254; FPGA in the Loop; Model-Based Design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Technology in Medicine and Education (ITME), 2012 International Symposium on
  • Conference_Location
    Hokodate, Hokkaido
  • Print_ISBN
    978-1-4673-2109-9
  • Type

    conf

  • DOI
    10.1109/ITiME.2012.6291476
  • Filename
    6291476