Thermal Aware Clocktree Optimization in Nanometer VLSI Systems Considering Temperature Variations

This paper proposed an accurate yet efficient clocktree synthesis algorithm that tolerates the temperature variation in the nanometer very large scale integration (VLSI) systems. Observing that there exists the correlation between input thermal power and temperature, we propose a clustered perturbation based parameterization to compactly generate a clocktree model considering the temperature variation. Moreover, using a structured and parameterized model reduction, an accurate worst case skew can be efficiently obtained from a transient simulation, which provides both nominal temperatures at those sinks and their sensitivities with respect to the changes of merging points. With the use of the sensitivities from the macromodel, a thermal aware routing based clocktree optimization is performed level by level. The experimental results show that the proposed algorithm reduces up to 1.7X- 5X worst case skew in comparison to the existing approaches.