A new architecture for coherent M-PSK receivers

In a series of papers in recent years new structures for coherent M-PSK (m-ary phase shift keying) receivers were suggested. These include structures for carrier phase detectors for the carrier PLL (phase lock loop), carrier PLL lock detectors, symbol timing error detectors, symbol synchronization PLL lock detectors, carrier and symbol PLL loop filters, and SNR (signal to noise ratio) estimators. Taken together, it can be said that these structures define a new architecture for coherent M-PSK receivers. This architecture has several unique characteristics: (a) it is very suitable for compact implementation within an FPGA (field programmable gate array) or an ASIC (Application Specific Integrated Circuit); (b) it is resilient to AGC (Automatic Gain Control) imperfections; (c) it is particularly optimized for implementation using fixed-point binary arithmetic. In this paper we review the aforementioned structures and the interrelationships between them and discuss various optimizations and implementation details of the proposed receiver architecture. Because of the suitability of the proposed architecture with regards to fixed-point hardware implementations, it is particularly suitable for low-power operation and high data rates, both of which are very important attributes in contemporary communications systems. Results obtained through hardware implementation of the proposed architecture are presented and are compared to theoretical results. We also briefly discuss possible applications of the proposed structures to other related modulations, such as D-MPSK (differential M-PSK), QAM (quadrature amplitude modulation), OMPSK (Offset MPSK), MSK (minimum shift keying), GMSK (Gaussian MSK), and other CPM modulations, as well as for hierarchical constellations and cognitive radio.