DoE simulations and measurements with the MicroDAC stress chip for material and package investigations

One major challenge for power and microelectronics system integration today is the assurance of reliability, very often mastered by a carefully tuned interplay of the still dissimilar materials that make up a package, first under optimized processing conditions, and then often under combined loading conditions. Therefore, not only during design but also during test and operation it would be desirable to in-situ monitor the stresses induced within a package onto a silicon die, as these thermo-mechanically induced stresses give rise to failure modes like solder fatigue, interface delamination and die cracking. In this vein the knowledge of the stress state would not only give much valued feedback to verify the simulations which are often used to predict lifetime based on material characterization. But it would also enable designers to study the behavior over time, revealing degradation mechanisms in the sense of a non-destructive failure analysis technique, so it could contribute to a better understanding of failure up to the point where the stress sensor could even be used as a lifetime monitor (health monitoring for electronic packages). The in-situ detection of failures in microelectronic packages in an experiment is still a big challenge. The reliability of most packages will be qualified by measuring the electrical resistance of daisy chain structures. The moment of failure in the electrical signals or the changes in the resistance are used for reliability or lifetime estimations. But the correlation of electrical resistance in the metallization and the packages or system reliability is very low. Extremely time-consuming investigation is needed to localize package failure after the experiment. Therefore, a chip, the MicroDAC stress chip, has been developed in a publicly funded project that is able to measure stress induced by thermo-mechanical loads. Different components of the stress tensor can be read out, as e.g. the in-plane stress difference and the in-plane- - shear stress on the chip surface within a 300 μm grid. This enables in-situ determination of the stress state even when the die is packaged and molded over. Residual stresses induced by processing steps as well as degradation within the materials or interfaces can thus be detected and measured. /1; 21. A further advantage is the simple read out procedure which needs only four wire bond or flip-chip bump connections. With this chip is it possible to get answers what happened with the package during the temperature cycling tests. How fast is the failure growing from one cycle to the next and when is the failure mechanism changing in the experiment? What is the influence of vibration or moisture on the stress?