Control Loops for the J-PARC RCS Digital Low-Level RF Control

The low-level radiofrequency control [1] for the Rapid Cycling Synchrotron of J-PARC [2], [3] is based on digital signal processing. This system controls the acceleration voltages of 12 magnetic alloy loaded cavities. To achieve a short overall delay, mandatory for stable loop operation, the data processing is based on distributed arithmetic in FPGA. Due to the broadband characteristic of the acceleration cavities, no tuning loop is needed., The RF system operates simultaneously with dual harmonics (h=2) and (h=4) [4] to handle the large beam current. The stability of the amplitude loops is limited by the delay of low pass FIR filters used after digital down conversion. The phase loop offers several operation modes to define the phase relation of (h=2) and (h=4) between the longitudinal beam signal and the vector-sum of the cavity voltages. Besides the FIR filters, we provide cascaded CIC filters with smoothly varying coefficients [5]. Such a filter tracks the revolution frequency and has a substantially shorter delay, increasing the stable operating region of the phase loops. The adaptive radial loop samples the orbit variation. Combined with a feed-forward of the dipole current the effects of measurement errors on the effective acceleration frequency program are reduced.