Title :
Through Silicon Via polymer filling for 3D-WLP applications
Author :
Bouchoucha, M. ; Chapelon, L.-L. ; Chausse, P. ; Moreau, S. ; Sillon, N.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
In this paper, polymer filling of medium density (40 μm diameter and 120 μm depth) via-last Through Silicon Via (TSV) is investigated. Firstly, a set of specifications for the polymer selection is established and discussed. Secondly, an adequate filling process and its optimization are developed. The polymer overburden thickness and planarization issues are also taken into account, since this polymer should also passivate the copper redistribution layer on the backside surface of the wafer. Material characterizations are then performed in order to obtain relevant properties concerning the polymer itself, surrounding materials and their interactions. To this end, several characterization techniques were investigated and adapted to our requirements such as dielectric spectroscopy, nanoindentation and 4-point bending test. Finally, thermo-mechanical simulations are performed to study stress and strain state induced by the presence of polymer in the TSV. These mechanical constraints are due to the coefficient of thermal expansion (CTE) mismatch between the involved materials. The parameters investigated in the previous part are used as inputs in these numerical simulations. The impact of the thermomechanical stress on the structure is then examined and compared to experimental stress and strain measurements.
Keywords :
bending; copper; nanoindentation; numerical analysis; passivation; planarisation; plastic packaging; polymers; thermal expansion; three-dimensional integrated circuits; wafer level packaging; 3D-WLP Applications; 4-point bending test; Cu; TSV; copper redistribution layer passivation; dielectric spectroscopy; nanoindentation; numerical simulations; planarization; polymer overburden thickness; size 120 mum; size 40 mum; strain state; stress state; thermal expansion coefficient; thermo-mechanical simulations; through silicon via polymer filling; wafer-level packaging; Passivation; Permittivity; Polymers; Silicon; Solvents; Through-silicon vias;
Conference_Titel :
Electronic System-Integration Technology Conference (ESTC), 2010 3rd
Conference_Location :
Berlin
Print_ISBN :
978-1-4244-8553-6
Electronic_ISBN :
978-1-4244-8554-3
DOI :
10.1109/ESTC.2010.5642998