Title :
Ultrafast compact CMOS dividers
Author :
Theis, Jean-Paul ; Schlimper, Harald
Author_Institution :
LG Semicon R&D Center, Willich, Germany
Abstract :
This paper introduces a new class of ultrafast and compact divider circuits. They are obtained by a systematic parallelization of a simple restoring division algorithm. Emphasis is put onto the stepwise parallelization methodology. Furthermore, a detailed discussion of implementational aspects is presented, including timing and layout. When, compared to SRT-schemes, these divider circuits allow a speed-up by a factor 2 to 3, while the cost is nearly identical. In particular, it is expected that double-precision IEEE Std. 756 floating-point division is performed within ca. 13 ns in 0.3 μm, CMOS technology
Keywords :
CMOS logic circuits; digital arithmetic; dividing circuits; parallel architectures; 0.3 mum; CMOS dividers; compact; divider circuits; floating-point division; layout; parallelization; restoring division; timing; ultrafast; Adders; CMOS technology; Circuits; Costs; Delay; Hardware; Image processing; Image restoration; Linear algebra; Research and development;
Conference_Titel :
Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-8186-8227-2
DOI :
10.1109/ICPADS.1997.652538
