An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

In this paper, we propose an efficient VLSI architecture which performs the two-dimensional (2D) discrete wavelet transform (DWT) of 9/7 filter for JPEG2000. Based on the modified lifting-based DWT algorithm, an efficient VLSI architecture for one-dimensional (1D) DWT is derived to reduce the hardware cost and shorten the critical path. The proposed 2D DWT architecture is composed of two 1D processors (row and column processors). Based on the line-based architecture, the column processor can start columnwise transform while only two rows have been processed. For an MxN image, only 5.5N internal memory is required for the 9/7 filter to perform the 2D DWT with the critical path of one multiplier. Finally, Verilog simulation results are presented to show that the proposed architecture in comparison with other existing architectures is fast and efficient for the 2D DWT computation.