DocumentCode
3201946
Title
Functional verification based on the EFSM model
Author
Fummi, Franco ; Marconcini, Cristina ; Pravadelli, Graziano
Author_Institution
Dipt. di Informatica, Univ. di Verona, Italy
fYear
2004
fDate
10-12 Nov. 2004
Firstpage
69
Lastpage
74
Abstract
The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults.
Keywords
automatic test pattern generation; fault diagnosis; finite state machines; formal verification; hardware description languages; logic testing; sequential circuits; EFSM model; finite state machine; functional verification; hard-to-detect fault; high-level ATPG; sequential circuits; Automata; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Hardware design languages; Observability; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
ISSN
1552-6674
Print_ISBN
0-7803-8714-7
Type
conf
DOI
10.1109/HLDVT.2004.1431240
Filename
1431240
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