Title :
Test quality for high level structural test
Author :
AI- Yamani, A. ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes A TPG faster and potentially reduces the size of the test set that needs to be applied. A variety of other techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This paper presents data obtained from applying a variety of test sets on the ELF35 test chip and recording the test escapes. The data presented show the test quality effect of using complex gates as fault sites. The paper also shows the impact of test compaction and reduced fault coverage on the test quality.
Keywords :
automatic test pattern generation; fault diagnosis; formal verification; high level synthesis; logic gates; logic testing; microprocessor chips; ELF35 test chip; automatic test pattern generation; complex high-level gates; digital chip; full adder; high level structural test; multiplexer; single-stuck-fault coverage test set; test quality; Adders; Automatic test pattern generation; Chip scale packaging; Circuit faults; Circuit testing; Cyclic redundancy check; Large scale integration; Libraries; Logic design; Logic testing;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Print_ISBN :
0-7803-8714-7
DOI :
10.1109/HLDVT.2004.1431250
