DocumentCode
3202559
Title
On equivalence checking between behavioral and RTL descriptions
Author
Fujita, Masahiro
Author_Institution
VLSI Design & Educ. Center, Tokyo Univ., Japan
fYear
2004
fDate
10-12 Nov. 2004
Firstpage
179
Lastpage
184
Abstract
In this paper we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed "attribute statements" in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are presented as well.
Keywords
high level synthesis; logic design; logic testing; RTL descriptions; behavioral level design; equivalence checking; interactive fashion; real life industrial design; register transfer level design; virtual controller; virtual datapath; Combinational circuits; Data analysis; Hardware; High level synthesis; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
ISSN
1552-6674
Print_ISBN
0-7803-8714-7
Type
conf
DOI
10.1109/HLDVT.2004.1431267
Filename
1431267
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