Feasibility study of low-swing clocking

This paper evaluates the feasibility of low-swing clocking under no performance degradation constraint. We consider flip-flops, logic and clock distribution network in our analysis. The preferred flip-flop topologies for low-swing clocking (low-V_Clk) are different from those normally used in a full-swing (high-V_Clk) design. Clock buffers are redesigned to accommodate reduced drive current under low-V_Clk. In order to maintain performance, logic and flip-flops must absorb increase in clock skew due to low-V_Clk. In a 64-bit ALU design, the optimal low-V_Clk design point is at the minimum energy-delay product (EDP) point of the high-V_Clk design, with no delay or energy penalty in the ALU itself. A 43% energy reduction achieved in the clock distribution network results in a 13% overall energy savings due to low-V_Clk, assuming that the clocking energy is 40% of the total energy tinder high-V_Clk. For performance targets of at least one FO4 inverter delay better than the min-EDP point, low-swing clocking becomes ineffective because of a high energy cost in logic that is spent to absorb increase in flip-flop delay and clock skew. Finally, low-V_Clk cannot achieve the peak performance of the high-V_Clk design due to slower flip-flops and higher clock uncertainty at low-V_Clk.