CMOS current-mode Euclidean distance circuit using Floating-Gate MOS transistors

A current-mode Euclidean distance circuit will be presented. In order to reduce the circuit complexity, a FGMOS (Floating Gate MOS) transistor will be used in the squarer circuit, whose accuracy is improved compensating the error introduced by the second-order effects. For this reason, an original technique based on a proper common-mode input voltage excitation of the squarer circuit will be proposed. The classic square-root circuit, designed using exclusively MOS transistors is replaced by a FGMOS implementation, having the advantage of a very large reducing of the circuit complexity, obtained by removing the necessity of using a threshold voltage extractor circuit.