Effect of Process Parameter Variation in Deposited Emitter and Buffer Layers on the Performance of Silicon Heterojunction Solar Cells

Heterostuctures of amorphous silicon (a-Si:H) and n-type crystalline silicon (c-Si) were investigated with special emphasis on the effect of emitter [p (a-Si:H)] and buffer layer [i (a-Si:H)] processing conditions. Boron (B)-doping in emitter layer sensitively affects performance of heterojunction solar cells without a buffer layer and controls valence band offset (DeltaE_V) at the hetero-interface. Insertion of 10 nm buffer layers passivate c-Si surface very efficiently albeit with an increased DeltaE_V and poor carrier transport across the heterojunction. Consequently, an open circuit voltage (V_oc) of 700 mV was achieved with low fill factor (FF). Buffer layers deposited at high H₂/SiH₄ ratio (R=40) and/or at higher temperature (300degC) improve FF (77%) but lead to lower V_oc (638 mV). Therefore, the emitter and the buffer layer process parameters play important roles to determine the band alignment and carrier transport across the a-Si:H / c-Si hetero-interface