Title :
Decimation filter design
Author :
Sokolovic, Miljana ; Jovanovic, Borisav ; Damnjanovic, Milunka
Author_Institution :
Dept. of Electron., Nis Univ., Serbia
Abstract :
Decimation filters´ architecture for an integrated power-meter is presented in this paper. It is based on parallel processing techniques and inherent pipelining and offers advantages in high speed operation, low power consumption and low complexity for VLSI implementation. The design process consists of several steps, and a full design procedure from the high level coefficients calculation to the synthesis phase performed using SE tools of Cadendce design system is given here. Digital filters are realized using Alcatel CMOS 0.35 technology and its library elements.
Keywords :
CMOS integrated circuits; digital filters; integrated circuit design; VLSI implementation; decimation filter design; high speed operation; inherent pipelining; integrated power-meter; low complexity; low power consumption; parallel processing techniques; CMOS technology; Computer architecture; Delta-sigma modulation; Digital filters; Digital signal processing; Finite impulse response filter; Frequency; Signal processing; Very large scale integration; Voltage;
Conference_Titel :
Microelectronics, 2004. 24th International Conference on
Print_ISBN :
0-7803-8166-1
DOI :
10.1109/ICMEL.2004.1314899
