A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS

This paper introduces a flash analog-to-digital converter with high power efficiency. Traditional voltage comparator is replaced by a novel comparison scheme in time domain: analog signal is converted by pulse width modulation block; trigger makes decision by comparing the modulated pulse width. Prototype circuit is designed in a 65-nm logic CMOS technology, achieving a sampling rate of 125-MS/s and an effective number of bits of 4.72. The power consumption is 367-μW under the power supply of 1-V; therefore Figure of Merit at 111-fJ/conversion step is realized.