Title :
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications
Author :
Vamvakos, Socrates D. ; Gauthier, Claude R. ; Rao, Chethan ; Canagasaby, Karthisha Ramoshan ; Choudhary, Prashant ; Dabral, Sanjay ; Desai, Shaishav ; Hassan, Mahmudul ; Hsieh, K.C. ; Kleveland, Bendik ; Mandal, Gurupada ; Rouse, Richard ; Saraf, Ritesh ;
Author_Institution :
MoSys Inc., Santa Clara, CA, USA
Abstract :
The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.
Keywords :
CMOS integrated circuits; field programmable gate arrays; jitter; phase locked loops; transceivers; CMOS; FPGA; SerDes transceiver; architectural technique; bit rate 2.488 Gbit/s to 11.2 Gbit/s; circuit technique; high-reliability system design; low-jitter LC PLL; low-leakage process; multiprotocol SerDes; performance impact mitigation; size 40 nm; system modeling approach; CMOS integrated circuits; Clocks; Decision feedback equalizers; Jitter; Phase locked loops; Receivers; Transmitters;
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2012.6291943
