• DocumentCode
    3202916
  • Title

    Optimization of short channel CMOS LNAs by geometric programming

  • Author

    Jin, Xiaoyu ; Hoe, David H K

  • Author_Institution
    Electr. Eng. Dept., Univ. of Texas at Tyler, Tyler, TX, USA
  • fYear
    2012
  • fDate
    5-8 Aug. 2012
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    Geometric programming is a method used to produce globally optimal circuit parameters with high computational efficiency. This method is applied to a short channel (90 nm and 180 nm) CMOS Low Noise Amplifier (LNA) design with common source inductive degeneration to obtain optimal design parameters for minimizing the noise figure. Geometric programming (GP) compatible functions have been determined to calculate the noise figure of short channel CMOS devices by taking into consideration channel length modulation and velocity saturation effects. Optimal design parameters (i.e., channel width and noise figure) from GP optimization are validated by comparing them with simulations obtained from Agilent´s Advanced Design Systems (ADS) software. Furthermore, tradeoff analyses have been performed to examine the influence of various design parameters such as quality factor and drain current on the design optimization. With the continuous downscaling of CMOS technologies, GP optimization offers high performance advantages in the optimal design of short channel CMOS LNAs.
  • Keywords
    CMOS analogue integrated circuits; Q-factor; circuit optimisation; geometric programming; integrated circuit design; low noise amplifiers; ADS software; GP compatible functions; advanced design systems; channel length modulation; common source inductive degeneration; drain current; geometric programming; globally optimal circuit parameters; low noise amplifier design; noise figure minimization; optimal design parameters; quality factor; short channel CMOS LNA optimization; size 180 nm; size 90 nm; tradeoff analysis; velocity saturation effects; CMOS integrated circuits; Logic gates; Noise; Noise figure; Optimization; Programming; Q factor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
  • Conference_Location
    Boise, ID
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4673-2526-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2012.6291944
  • Filename
    6291944