Title :
Design and modeling of on-chip electrostatic discharge (ESD) protection structures
Author :
Liou, Juin J. ; Gao, Xiaofang
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Central Florida, Orlando, FL, USA
Abstract :
Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.
Keywords :
SPICE; electrostatic discharge; equivalent circuits; integrated circuit design; integrated circuit reliability; Cadence SPICE; ESD circuit simulation; computer-aided design too; critical reliability concern; human body model; microchips; on-chip electrostatic discharge protection structures; transmission line pulsing technique; Application software; Biological system modeling; Circuit simulation; Design automation; Electrostatic discharge; Electrostatic measurements; Protection; Robustness; SPICE; Standards development;
Conference_Titel :
Microelectronics, 2004. 24th International Conference on
Print_ISBN :
0-7803-8166-1
DOI :
10.1109/ICMEL.2004.1314905
