DocumentCode
3203110
Title
A Class-D stage with harmonic suppression and DLL-based phase generation
Author
Fritzin, Jonas ; Mesgarzadeh, Behzad ; Alvandpour, Atila
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden
fYear
2012
fDate
5-8 Aug. 2012
Firstpage
45
Lastpage
48
Abstract
This paper presents a Class-D stage with 3rd harmonic suppression operating at 2VDD(i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Ω load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.
Keywords
CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; delay lock loops; driver circuits; harmonics suppression; waveform generators; DLL based phase generation; class-D stage; driver stage; frequency 1 GHz; harmonic suppression; nominal supply voltage; power dissipation; voltage 1 V; Clocks; Delay; Generators; Harmonic analysis; Harmonics suppression; Power harmonic filters; Radiation detectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location
Boise, ID
ISSN
1548-3746
Print_ISBN
978-1-4673-2526-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2012.6291953
Filename
6291953
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