Title :
Impact of gate-leakage currents on CMOS circuit performance
Author :
Marras, A. ; De Munari, Ilaria ; Vescovi, Davide ; Ciampolini, Paolo
Author_Institution :
Dipt. di Ingegneria dell´´Inf., Parma Univ., Italy
Abstract :
Ultra-thin gate dielectrics are exploited in fabrication of MOSFET´s featuring channel lengths in the decananometer range: the ITRS indicates that oxide thickness in the order of 1 nm will be used in 2005 for ultra-short CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of Direct-Tunneling (DT) current on the behaviour of a wide variety of CMOS circuits is presented, based on a simulation strategy aimed at predicting the correlation of major performance indices with oxide thickness.
Keywords :
CMOS integrated circuits; dielectric thin films; integrated circuit modelling; integrated circuit reliability; leakage currents; tunnelling; 1 nm; CMOS circuit performance; gate-leakage currents; oxide thickness; simulation strategy; ultra-thin gate dielectrics; CMOS technology; Circuit optimization; Circuit simulation; Dielectric devices; Fabrication; Gate leakage; Leakage current; MOSFETs; Moore´s Law; Tunneling;
Conference_Titel :
Microelectronics, 2004. 24th International Conference on
Print_ISBN :
0-7803-8166-1
DOI :
10.1109/ICMEL.2004.1314913
