Title :
Hot-carrier induced degradation of offset gated polysilicon TFTs
Author :
Hatzopoulos, A. ; Dimitriadis, C.A. ; Pananakakis, G. ; Ghibaudo, G. ; Kamarinos, G.
Author_Institution :
Dept. of Phys., Thessaloniki Univ., Greece
Abstract :
Hot-carrier effects are investigated in offset gated polysilicon thin-film transistors of channel length L = 10 μm and offset length ΔL = 0.5 and 1 μm, and compared with those of self-aligned devices. The gate and drain bias conditions for maximum device degradation were determined from substrate current measurements. In offset gated devices, the experimental data show that the threshold voltage and the on-state current degrade exhibiting a "staircase-like" behavior with stress time. The results are explained in terms of grain boundary trap filling, with electrons generated by impact ionization in successive small offset regions from the drain end.
Keywords :
defect states; elemental semiconductors; grain boundaries; hot carriers; interface states; silicon; thin film transistors; 0.5 micron; 1 micron; 10 micron; Si; drain bias conditions; gate bias conditions; grain boundary trap filling; hot-carrier induced degradation; impact ionization; maximum device degradation; offset gated polysilicon TFTs; self-aligned devices; staircase-like behavior; stress time; substrate current measurements; Current measurement; Degradation; Electron traps; Grain boundaries; Hot carrier effects; Hot carriers; Stress; Substrates; Thin film transistors; Threshold voltage;
Conference_Titel :
Microelectronics, 2004. 24th International Conference on
Print_ISBN :
0-7803-8166-1
DOI :
10.1109/ICMEL.2004.1314925