16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor

This paper describes a 16-bit Logarithmic Signal Processor and its implementation using Clocked Adiabatic Logic (CAL). The proposed architectures for Lin2Log and Log2Lin converters are based on a linear interpolation algorithm. The CAL-Logarithmic Signal Processor has been designed using an AMS 0.35 μm CMOS process and consumes an area of 7.3 μm². Spice simulations have shown that the circuit can operate at frequencies up to 250MHz and energy calculation have indicated 211.34 pJ power consumption at the maximum operating frequency.